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IP Core
Please submit IP Cores to tkeller@greatrivertech.com
Great River Technology’s (GRT) ARINC 818 transceiver core provides an easy way to implement ARINC 818 compliant interfaces in Xilinx V2, V2Pro, V4 and V5 PLDs. The core uses Xilinx Rocket IO transceivers (MGTs or GTP tiles) to achieve ARINC 818 interfaces up to 3.1875 Gbps (4.25 Gbps coming soon). The core can be used for transmit only, receive only, or for transmit and receive applications. The core has many flexible compile time settings allowing for various link speeds, line segmentations, and line synchronization methods. The core can be configured for various resolutions and pixel packing methods. Ancillary data can use default values set at compile time or data can be updated in real time via register interface. Click here for a product brief |